1. Field of the Invention
The present invention generally relates to storage devices and more particularly to an improved process for forming a strap in a deep trench storage device.
2. Description of the Related Art
Trench storage cells are used in dynamic random access memory (DRAM) products due to the high degree of planarity obtainable with the trench structure during chip processing. One of the challenges associated with trench DRAM processing is the formation of an electrical connection between the trench capacitor and the diffusion region of the array device pass transistor.
Conventionally, as shown in FIG. 1F, a "buried strap" 120 connection is made between the top of a trench 100 and a diffusion region (i.e., drain 134) of a transistor 130. The buried strap 120 connection eliminates the requirement for a distinct lithographic patterning level.
More specifically, the conventional process of forming a buried strap is illustrated in FIGS. 1A-1F. FIG. 1A illustrates a trench 100 which is formed in a substrate 101 to a depth greater than 5 .mu.m below a pad silicon nitride layer 104 by conventional means such as photolithography and dry etching using a mixture of gases which may include Cl.sub.2 Hbr, O.sub.2, N.sub.2, NF.sub.3, SF.sub.6, and CF.sub.4. Then a collar dielectric oxide 103 (such as silicon dioxide or silicon oxynitride) is deposited over the pad nitride 104 and trench 100.
As shown in FIG. 1B, the collar oxide is etched in an anisotropic dry etching process, such as reactive ion etching (RIE), using a mixture of gases which may include some portions of CHF.sub.3, Ar, O.sub.2, C.sub.4 F.sub.8, and CO. The anisotropic dry etch, or sidewall spacer etch, removes material in a vertical direction at a higher rate than it removes material in the horizontal direction. Therefore, the highly selective anisotropic spacer etch will leave material along the sidewall of the trenches, and remove material from the horizontal surfaces.
As shown in FIG. 1C, the trench is then filled with a second level of polysilicon 110. The second level of polysilicon is then recessed to a depth of less than using 0.1 .mu.m a dry or wet etch. Also, as is well known to those ordinarily skilled in the art, a LOCOS (e.g., local oxidation of silicon) collar may be formed followed by a recess to achieve the structure shown in FIG. 1D. Then, as shown in FIG. 1D, the collar oxide is etched down to the second level of polysilicon 110 using a wet etch, such as HF.
A third level of polysilicon 120 is deposited and the structure is planarized and recessed below the pad nitride 104 using a dry etch process, as shown in FIG. 1E. The third level of polysilicon 120 becomes the strap which contacts the diffusion area of the transistor.
The structure shown in FIG. 1E is formed in conjunction with a transistor 130, such as a metal oxide semiconductor field effect transistor (MOSFET), which is illustrated in FIG. 1F. More specifically, the transistor includes a gate 131, a gate oxide 132, a source region 133, a drain region 134 and a shallow trench isolation (STI) region 135. The process of forming such a transistor 130 is well known to those ordinarily skilled in the art.
The third level of polysilicon 120 is the strap and forms an electrical connection between the first and second layers of polysilicon 102, 110 and the source/drain 134 of the transistor 130. This type of strap is known as a buried strap because it exists below the top surface of the substrate 101. By utilizing such a buried strap, the size of the semiconductor device can be reduced and, since an external strap is not required, the chance of damage to other structures within the semiconductor device is also reduced.
However, conventional processes indirectly cause the strap 120 to be recessed 121 with respect to the silicon 101 and pad nitride 104 surface when the active area isolation (e.g, the STI region 135) is formed. This non-planarity 121 causes severe problems during the subsequent lithography and disrupts overlay tolerance when printing the critical active area (AA) structures in the array.
Further, the conventional process of manufacturing deep trench DRAM structures does not allow accurate control of the strap depth. If the strap is too deep it limits the scaling and array threshold voltage (Vt) control of the active transfer device. The depth of the strap is conventionally controlled by the difference between the depth of the recess of the second polysilicon layer 110 and the depth of the recess of the third polysilicon layer 120 in the array. However, controlling the depth of the strap in this manner causes the strap resistance to be a function of not only both the recess depths, but also of the strap wet etch, which substantially reduces the accuracy of the strap depth.
While some conventional methods allow vertical scaling of the buried strap using a pad nitride pull back to form the strap, such methods cause non-planar wafers to be formed after the deep trench sector and involve significant modifications in the active area processing to ensure the prevention of strap erosion.
Therefore, there is need for a system which will eliminate the lithographic problems caused by the uneven surface of the trench and which allows more precise control over the depth of the strap.